With continuous shrinking of a feature size of a semiconductor device in proportion by Moore's Law, integration of chips continues to be increased to cause negative effects such as a short-channel effect, a coulomb scattering and the like, which brings a bottleneck for the traditional planar MOSFETs in a development of semiconductor technology to the 22 nm process. As a solution for such a problem, three-dimensional FinFET gradually becomes a mainstream technique. During a process tending to a smaller node, the filling of the metal gate in a gate-last process meets a significant challenge. A traditional PVD technique has its own inherent limitations. At present, atomic-layer deposition has become the best solution for metal gate deposition, continued miniaturization of CMOS device and accompanying back gate trench filling.
In addition, a threshold voltage of the semiconductor device is related to the work function of a material for the gate electrode. In a traditional process ofr manufacturing a semiconductor device, it usually uses a single polysilicon gate design to simplify the manufacturing process and to save production costs. When the CMOS technology is developed to 45 nm, in order to reduce the gate leakage current, a high-K gate dielectric is introduced into the semiconductor manufacturing process. However, a traditional polysilicon gate contacting with polysilicon will lead a polysilicon depletion effect and Fermi level pinning effect, etc., which seriously affects device performance, so it needs a new type of gate material. Metal gate has a lower resistivity and is considered as the preferred material for the gate.
In CMOS circuits, there are different functional circuit modules, such as high performance computing modules and low power consumption modules. Different circuit modules require different threshold voltages, i.e. different metal work functions. Therefore, it is urgently required to design a material with a variable work function as a gate to adjust the work function of the same system material during the atomic layer deposition in the process for manufacturing a transistor to obtain the expected threshold voltage characteristic of the device.